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    2020 Design Engineer internship - 5-6 months

    • 17406
    • Design Engineering
    • Interns/Students
    • Physical Design
    • Physical Design - Engineering
    • France
    • Sophia Antipolis


    We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class.

    Job Description

    Arm Physical Design Group (PDG) delivers the most comprehensive and advanced physical IP solution including Standard Cell, Embedded Memory Compilers, Interface IP and Processor Optimization Pack (POPs).

    Our Physical IP deliver optimized performance, power and area results and are a key value to boost performance of latest Arm processor cores and pioneer the implementation of power efficient products for the future.

    These 4 internships are a rare opportunity to be a part of talented and highly motivated team and to influence the development of leading edge Memories that will be used extensively in a wide variety of devices. 

    [2020-LOG-1] - Exploration of Flip-Flop design with sub-threshold technics

    Sub-threshold voltage (STV) techniques adopt aggressive supply voltage scaling, below the threshold voltage of transistors, which is considered a possible solution for targeting the energy-constrained system.

    However, various challenges can be observed in STV region, such as: process variation, performance degradation etc.
    You will learn these technics and will explore – on structure like flops, how to reduce the performances losses, maintain a good energy efficiency, and limit the process variation impact.

    With this internship: you will have the opportunity to implement (schematic, layout) and analysis (simulation) the state-of-the-art sub threshold circuits. Joins us and explore novel methodology to address the challenges of STV circuits! 

    [2020-LOG-2] - Overlay structure impact studies to improve Standard Cells characterization

    To characterize the logic libraries, we place each function into a realistic environment, so that the physical effect is took into consideration during timing measurements.

    The goal of that internship is to study these effects and define a methodology to accurately measure resulting timing impact. This internship is in direct touch with the layout.

    You will see the impact of neighbouring shape on the cells performance, you will discover how standard-cells are build and the impact they have on the overall circuit performances.

    You will carry investigation, and be in touch with EDA vendor to test, feedbacks their tool and guide the adaptations you may need.

    Job Requirements

    What skills, experience and qualifications do I need?

    We are looking for students in their last year of Masters (BAC+5 or equivalent), in Electronic Engineering or equivalent relevant field, and available for 5 to 6 months.

    • Curious, willing to learn and discover.
    • Interesting in standard cell layout & design.
    • Ability to communicate in English in writing (mails, documentation) and during meetings. 

    Other desirable skills include:

    • Knowledge of Cadence Virtuoso
    • Familiar with Spice language or equivalent
    • Interest in software programming or scripting


    ARM Benefits


    Your particular benefits package will depend on position and type of employment and may be subject to change. Your package will be confirmed on offer of employment. Arm’s benefits program provides permanent employees with the opportunity to stay innovative and healthy, ensure the wellness of their families, and create a positive working environment.

    • Annual Bonus Plan
    • Discretionary Cash Award
    • Supplementary pension
    • Private Medical Insurance (employee & family)
    • Life Insurance
    • Holiday, 25 days annual leave
    • Sabbatical, 20 paid business days every four-years of service
    • Volunteering, One (1) paid working day each year (TeamARM)
    • Others, free car parking, luncheon vouchers & Public Transport Pass reduction, team and social events

    About Arm

    Arm® technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. From the unmissable to the invisible; our advanced, energy-efficient processor designs are enabling the intelligence in 86 billion silicon chips and securely powering products from the sensor to the smartphone to the supercomputer. With more than 1,000 technology partners including the world’s most famous business and consumer brands, we are driving Arm innovation into all areas compute is happening inside the chip, the network and the cloud.

    With offices around the world, Arm is a diverse community of dedicated, innovative and highly talented professionals. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we encourage our people to share their unique contributions to Arm's success in the global marketplace.

    About the office

    The staff at the Arm Sophia Antipolis design center is mostly focused on CPU design. Sophia Antipolis is a technology park that’s surrounded by a large national park, with wild boar that live within the city and can be seen strolling through the tech park. It’s conveniently located a quick 30 minute drive southwest of Nice, 45 minutes to Monaco, and only 20 minutes to Cannes.

    Sophia Antipolis, France
    Arm France SAS
    25 Allée Pierre Ziller
    Le Paros
    BP 70124
    F-06903 Sophia Antipolis Cedex

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