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    Search

    Graduate Engineer

    • 11468
    • Hardware Engineering
    • Experienced Professionals
    • Physical Design
    • Physical Design - Engineering
    • India
    • Bangalore

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    We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class.

    Job Description

    Role Purpose

    The Physical IP Division inside ARM creates Physical IPs of various types like Standard Cells, Memory, and Interface which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180nm to 10nm and research work on 7nm solutions is happening at various ARM design centres worldwide.
    A dedicated team of experienced professionals in software, methodology and flow development aids this process of creating Physical IPs for leading edge chips. Forming part of the ARM Physical IP Division, the Modelling and Methodologies Group develops Front end models for Standard Cells, Memory and Interface physical IP as well as creates methodologies to validate the physical IP. The front end model development involves creation of Simulation, ATPG, Low Power views which gets used during SoC IP validation. The group also focuses on developing methodologies like Correlation, Simulation, Synthesis, DFT, ATPG, Logic Equivalence, Place and Route etc. that makes the IP robust and high quality while reducing the cost with improved efficiency.


    Role & Responsibilities

    Modelling

    The candidate’s responsibility includes development, validation and maintenance of the Verilog simulation models for physical IP. Along with that candidate would have complete ownership of the DFT and ATPG models that are used in SoC flow. The role offers a potent opportunity to interact with accomplished circuit designers worldwide for design of best in class Physical IPs on the latest technologies nodes like 16nm, 10nm, 7nm etc. Candidate would serve as interface between the engineering teams, external customers and the third party EDA vendors to track resolution of issues associated with front end validation tools like Functional simulators, LEC, ATPG, STA etc.
    IP Validation
    The candidate would be involved in defining/updating the methodology for validation of Physical IPs, understanding the requirements of circuit designers spanning across multiple ARM sites worldwide. He is expected to work closely with software team for the implementation and validation of the flows in order to create most efficient and high quality solutions for the users. The candidate would be provided opportunity to develop his skill sets to develop his expertise in front end or back end flows. He is expected to be proactive in supporting the flows developed by the design automation team.

    Job Requirements

    Qualification & Experience

    • Bachelors or Master’s Degree in Electronics Engineering or equivalent
    • 0-1 years of engineering experience in Verilog modelling and verification 

    Characteristics & Requirements

    • Quick learner, good problem solving and debugging skills
    • Willingness to be flexible and accept new challenges
    • Capable of working as a team player or independently
    • Good analytical and reasoning skills
    • Enthusiastic and self-motivated
    • Good communication skills

    Essential Technical Experience

    • Good understanding of digital circuits fundamentals and SoC concepts
    • Working knowledge of scripting tools (TCL, Perl)

    Desirable Technical Experience

    • Experience with Verilog modelling and verification
    • Experience with Frontend flows like Simulation, Synthesis, ATPG and Logic Equivalence

    ARM Benefits

    Benefits

    Your particular benefits package will depend on position and type of employment and may be subject to change. Your package will be confirmed on offer of employment. ARM’s benefits program provides permanent employees with the opportunity to stay innovative and healthy, ensure the wellness of their families, and create a positive working environment.

    • Annual Bonus Plan
    • Discretionary Cash Award
    • Contributory Pension
    • Insurance, Medical, Life & Personal accident
    • Holiday, 25 days annual leave
    • Sabbatical, 20 business days every four-year of service
    • Volunteering, One (1) paid working day each year (TeamARM)
    • Others, subsidized meal, gym, team and social events

    About Arm

    Arm® technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. From the unmissable to the invisible; our advanced, energy-efficient processor designs are enabling the intelligence in 86 billion silicon chips and securely powering products from the sensor to the smartphone to the supercomputer. With more than 1,000 technology partners including the world’s most famous business and consumer brands, we are driving Arm innovation into all areas compute is happening inside the chip, the network and the cloud.

    With offices around the world, Arm is a diverse community of dedicated, innovative and highly talented professionals. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we encourage our people to share their unique contributions to Arm's success in the global marketplace.

    About the office

    The ARM Bangalore office employs staff from the Architecture & Technology, CPU, Physical Design, Systems & Software and Administrative Support teams. Located at a height of over 900 m (3,000 ft) above sea level, Bangalore is known for its pleasant climate throughout the year which makes it suitable for a variety of outdoor sports in the numerous parks and gardens that dot the city.

    Bangalore, India
    ARM Embedded Technologies Private Ltd.
    Bagmane World Technology Center - SEZ
    Citrine Block, 5th and 6th Floor
    Marathahalli Outer Ring Road,
    Mahadevapura,
    Bangalore - 560 048.

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