Arm Physical Design Group (PDG) delivers the most comprehensive and advanced physical IP solution including Standard Cell, Embedded Memory Compilers, Interface IP and Processor Optimization Pack (POPs).
Our Physical IP deliver optimized performance, power and area results and are a key value to boost performance of latest Arm processor cores and pioneer the implementation of power efficient products for the future.
These 4 internships are a rare opportunity to be a part of talented and highly motivated team and to influence the development of leading edge Memories that will be used extensively in a wide variety of devices.
[2020-LOG-1] - Exploration of Flip-Flop design with sub-threshold technics
Sub-threshold voltage (STV) techniques adopt aggressive supply voltage scaling, below the threshold voltage of transistors, which is considered a possible solution for targeting the energy-constrained system.
However, various challenges can be observed in STV region, such as: process variation, performance degradation etc.
You will learn these technics and will explore – on structure like flops, how to reduce the performances losses, maintain a good energy efficiency, and limit the process variation impact.
With this internship: you will have the opportunity to implement (schematic, layout) and analysis (simulation) the state-of-the-art sub threshold circuits. Joins us and explore novel methodology to address the challenges of STV circuits!
[2020-LOG-2] - Overlay structure impact studies to improve Standard Cells characterization
To characterize the logic libraries, we place each function into a realistic environment, so that the physical effect is took into consideration during timing measurements.
The goal of that internship is to study these effects and define a methodology to accurately measure resulting timing impact. This internship is in direct touch with the layout.
You will see the impact of neighbouring shape on the cells performance, you will discover how standard-cells are build and the impact they have on the overall circuit performances.
You will carry investigation, and be in touch with EDA vendor to test, feedbacks their tool and guide the adaptations you may need.