Arm Physical Design Group (PDG) delivers the most comprehensive and advanced physical IP solutions including Standard Cells, Embedded Memory Compilers, Interface IP and Processor Optimization Pack (POPs). Our Physical IP deliver optimized performance, power and area results and are key to further push performance of latest Arm processor cores and pioneer the implementation of power efficient products for the future.
These 4 internships are a rare opportunity to be part of talented and highly motivated team and to influence the development of leading-edge memories that will be used extensively in a wide variety of devices.
[2020-MEM-1] - Optimization techniques accelerating electrical simulations for high capacity memory
Emerging memories are challenging in many aspects. Getting to sustainable simulation runtimes is
one of these challenges we need to overcome. Memory capacities are increasing, architecture complexity increases and involves mixed-signals circuits. All these novelties are leading to explore new ways of simulation setup. The internship will be structured around several phases: Bibliographic study required for exploring the entire field of simulation techniques, then understand memory architecture. The intern will have to tackle transistor level simulation, develop and apply in-house netlist reducer, and explore block level optimizations for simulation partitioning. This project requires to deploy a variety of techniques and tools to enable disruptive ideas to ultimately improve run-time simulation for high capacity memories.
[2020-MEM-2] - Charge pump and regulator design suitable for Nonvolatile Memories
Power consumption is today a key figure of merit for low power applications like medical IoT, environmental sensors and mobile devices. The voltage scaling is a widely used technic to provide
functionality of memories in extreme conditions. The aim of this internship will be to focus on the
charge pump architecture designs suitable for emerging nonvolatile memories (NVM). The intern will first analyse the state of the art of the charge pump and regulator designs. Following milestone will be to identify an optimized solution in term of performance, power and area based on the NVM requirements. You will need to consider the memory compiler constraints in order to tune and fully validate your design strategy. Working on advanced technology node (28nm,22nm,7nm) to make all experiments through the memory group, you will be able to improve your design and simulation skills as an Analog Design Intern.
[2020-MEM-3] Micropower Analog Bias Tailored for Emerging Memory Applications
Analog bias circuits are widely used to generate stable and accurate voltage/current references for a variety of systems: Memories, PLLs, ADC/DAC…
Power consumption is a key figure of merit for low power applications like medical, IoT, environmental sensors and mobile devices. The aim of this internship is to develop innovative micropower analog bias architecture suitable for emerging nonvolatile memories (NVM).
This internship will be organized around several phases: The first phase will be related to the state-of-the-art study, required for exploring analog bias architectures and identify the performance bottlenecks. Then, propose an architecture optimized in terms of performance, power, area and testability. And finally, validate the proposed architecture through electrical simulations using advanced technology nodes (FinFET/FD-SOI: 28nm and below).
As an Analog Design Intern for memory team, you will be able to gain experience in the design, simulation and analysis of micropower analog bias tailored for memory applications.
[2020-MEM-4] PVT-compensated delays for NVM self-timing circuit
The self-time circuit is a key element of a memory architecture, it cadences read and write memory operations and is used to control power consumption. The aim of this internship is to design a Process, Voltage, Temperature compensated self-time circuitry suitable for emerging non-volatile memories (NVM). The internship will be organized around several phases: The first phase will be related to the state-of-the-art study, required for exploring non-volatile memories and different solutions used for self-time circuits, then propose a robust Process, Voltage, Temperature compensated self-timing solution to overcome timing variability issue.
As Analog Design Intern inside the memory team, you will be able to improve your analog design skills, and you will be gaining an experience in non-volatile memories.