Do you want to help Arm and its partners to build outstanding products?
Arm Sophia Antipolis design centre is located in one of the most appealing parts of France, at the heart of Europe’s largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this outstanding design centre has delivered leading products from Arm’s Cortex (TM) processor family. These CPUs power some of the world’s best-seling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.
Now, you have an opportunity to take part in the development of the next generation of processors that will appear in the most desirable products over the next 3 years. The local design team is a good combination of very expert engineers and some of the most enthusiastic and hardworking graduates, coming from the best engineering schools. Collectively, the team is highly creative, collaborative, delivery orientated and committed.
You will be able to work closely with our hardworking and experienced engineers to help design ground-breaking technology. You will gain knowledge and tackle challenges while being able to encounter opportunities to work on all aspects of product development.
We want to make sure that every intern learns about different aspects of our work and grows their knowledge, that is why you will work in a team on real projects from day one, with guidance from expert engineers, and also have dedicated time for personal development.
You will be part of the CPU verification team and verify IP to the highest quality standards using a wide range of methodologies from constrained random simulation to real applications on emulation or FPGA platforms. Innovative formal methods are also at the heart of Arm verification methodology.
You will develop scripts, tools, models and test benches using various programming languages such as System Verilog, C, C++ and Python.
Several subjects are available and described below. Choose the one(s) you prefer and indicate them in your application. Only one student will work on a given subject, followed by a dedicated experienced engineer.
[REF 2020-V-1] QUALITY CHECK AUTOMATION OF A HIGHLY CONFIGURABLE TEST GENERATOR
Modern CPU features and performance lead to growing verification complexity. Stimulus generators are getting bigger and bigger to properly stress all the design functionalities. How can we guarantee the quality of these stimuli?
The goal of this internship is to ensure that test generation works as expected by monitoring smart statistics collected during test runs.
You will first develop a software infrastructure as efficient as possible to collect and visualize test metrics. A database will then be setup to monitor and automatically assess the quality of a huge set of tests. Data analysis techniques such as machine learning will be investigated to correlate test outputs to inputs.
[REF 2020-V-2] VERIFY MEMORY SYSTEMS USING INNOVATIVE FORMAL METHODS
How can we use innovative formal methods to verify data hazard in a modern application CPU memory system?
Modern application CPUs implement complex and optimized memory systems to push performance forward. To that end, data hazard is one of the micro-architecture key element to guarantee the correctness and such a level of performance.
The goal of this internship is to use formal verification methods to verify memory coherency issues caused by data hazard in a memory system.
[REF 2020-V-3] WAVEFORM EXTRACTION ON FPGA USING INNOVATIVE ARM TOOLS
FPGA are now extensively used at Arm for bug hunting in our CPUs but debugging an FPGA can be frustrating because of a lack of adequate internal visibility.
Arm already provides an FPGA debug solution able to extract CPU execution trace and monitor SVA. The goal of this internship is to go further and develop a highly efficient signal capture infrastructure for waveform extraction on FPGA.
You will start with a simple design in simulation. Then, you will investigate solutions to go further and increase the number of signals to be captured and the number of samples to be recorded considering techniques such as compression. Trials will be done on FPGA with real CPUs.
[REF 2020-V-4] IMPROVE PPA (POWER-PERFORMANCE-AREA) IN CPUs USING FORMAL TECHNIQUES
Arm CPUs are highly optimized thanks to designers’ expertise and synthesis tools. However, these designs also grow in size and complexity, making these optimizations more and more difficult.
The goal of this internship is to identify and implement new techniques based on formal methods that will either help with optimization or even automatically perform optimizations for PPAs
You will learn about formal verification capabilities and main design techniques used for PPA. You will investigate known blockers to achieve better PPAs.
You will then select some of these blockers and provide solutions using formal techniques. You will apply these techniques to real CPU designs and provide a comparison of the PPAs before and after optimization.
[REF 2020-V-5] EXPLORE C-RTL CO-VERIFICATION USING FORMAL TECHNIQUES
CPUs are developed at Register Transfer Level (RTL) in dedicated hardware languages. However, for a modern CPU, a lot of code around the RTL is written in higher-level languages like C for simulation testbenches, models, etc.
Even though formal verification is mainly focused on RTL verification, there are tools that allow us to formally verify C and RTL programs together.
The goal of the internship is to study the most useful use cases and evaluate tool performances on real CPU features such as branch prediction or floating-point computation.
[REF 2020-V-6] ADAPT VERIFICATION TECHNIQUES USED ON CORTEX-A PROCESSORS TO A CORTEX-M
Growing M-class CPU performance drastically increases logic complexity. Bugs are more and more triggered by a combination of complex instruction sequences and timings.
The goal of this internship is to evaluate, integrate and extend the verification methodology used on high-end application CPUs to Cortex-M CPUs.
You will get familiar with the Arm architecture and the CPU micro architecture to identify sensitive areas. You will then generate software to push an existing Cortex-M CPU to the limit. You will finally compare the results with the current test infrastructure.