Do you want to help Arm and its partners to build outstanding products?
Arm Sophia Antipolis design centre is located in one of the most appealing parts of France, at the heart of Europe’s largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this outstanding design centre has delivered leading products from Arm’s Cortex (TM) processor family. These CPUs power some of the world’s best-selling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.
Now, you have an opportunity to take part in the development of the next generation of processors that will appear in the most desirable products over the next 3 years. The local design team is a good combination of very expert engineers and some of the most enthusiastic and hardworking graduates, coming from the best engineering schools. Collectively, the team is highly creative, collaborative, delivery orientated and committed.
You will be able to work closely with our hardworking and experienced engineers to help design groundbreaking technology. You will gain knowledge and tackle challenges while being able to encounter opportunities to work on all aspects of product development.
We want to make sure that every intern learns about different aspects of our work and grows their knowledge, that is why you will work in a team on real projects from day one, with guidance from expert engineers, and also have dedicated time for personal development.
Meeting Area, Frequency, and Power requirements with a reasonable runtime is one of most challenging activities we encounter when developing CPUs.
On the soft IP market, we must also be as realistic as possible to ensure a good correlation with real silicon.
As Implementation engineers, we work with advanced EDA tools to model real physical environments of CPUs while targeting aggressive goals on advanced process nodes (7nm and below).
Join us and influence CPUs design, implementation methodology, and basic building block architecture (RAMs and standard cells).
Several subjects are available and described below. Choose the one(s) you prefer and indicate them in your application. Only one student will work on a given subject, followed by a dedicated expert engineer.
IN-DEPTH POWER OPTIMIZATION OF ADVANCED ARM CPU
Power consumption is a key parameter for all CPUs.
There are many ways to achieve low power and all of them will impact other key parameters such as area or frequency.
This internship will look at both modifying the CPU microarchitecture and using implementation flow features to improve dynamic and static power.
Using leading edge tools and methodology, you will analyse microarchitecture changes such as clock gating or data gating and find the correct trade-off to not impair frequency.
You will also investigate state-of-the-art CPU implementation flows and propose/adjust settings to obtain extra power benefits.
With this internship, you will have the opportunity to gain both knowledge on design for power efficiency and CPU implementation flow
[REF 2020-I-2] COMPARATIVE PHYSICAL IMPLEMENTATION OF ADVANCED ARM CPU
Pushing frequency, power efficiency, and optimizing area of a specific RTL IP is a central task in CPU development.
The goal of this internship is to set up and analyse the results of several CPU implementation flows from different tool vendors. The expected end results are comparative strengths and weaknesses of the studied variants.
With this internship, you will have the opportunity to learn CPU implementation flows in depth by adapting and using state-of-the art implementation flow from several tool vendors.
While interacting with skilled implementation engineers and EDA tool vendors, you will be responsible for getting the best possible results out of each flow on the next generation CPU.
You will have to examine the results compare them to reference data, and clearly articulate benefits and drawbacks of each approach.
Metrics to be analysed contain, among others, frequency, area, dynamic and static power consumption, routing congestion and errors, runtime, memory usage, and ease of use for PPA debug.
[REF 2019-I-3] NEXT GENERATION CPU INNOVATIVE STORAGE STRUCTURE
At the crossroad between CPU design, CPU implementation, and CPU Design For Test, you will have to compare area/frequency of storage structures using either DFF, RAMs, or latches.
During this internship, you will:
- Understand existing CPU storage units using either DFF or RAMs.
- Evaluate which one can be replaced by latch-based storage.
- Understand MBIST interfaces and connections and how it can be used to test latch-based storage.
- Propose code in Verilog and analyse area trade-off for different variants of this test interface, including in-depth analysis on how to implement efficiently a latch array.
With this internship, you will have the opportunity to do both Verilog coding and physical implementation on a next generation CPU.