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    2020 Engineering Internship CPU Implementation

    • 16765
    • Hardware Engineering
    • Interns/Students
    • Central Engineering - CPU
    • Central Engineering - CPU Engineering
    • France
    • Sophia Antipolis


    We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class.

    Job Description


    Do you want to help Arm and its partners to build outstanding products? 

    Arm Sophia Antipolis design centre is located in one of the most appealing parts of France, at the heart of Europe’s largest and most dynamic technology park. Surrounded by mountains and the Mediterranean Sea, this outstanding design centre has delivered leading products from Arm’s Cortex (TM) processor family. These CPUs power some of the world’s best-selling smartphones, tablets and gaming systems, using technology that has taken user experience and performance to another level.

    Now, you have an opportunity to take part in the development of the next generation of processors that will appear in the most desirable products over the next 3 years. The local design team is a good combination of very expert engineers and some of the most enthusiastic and hardworking graduates, coming from the best engineering schools. Collectively, the team is highly creative, collaborative, delivery orientated and committed. 

    You will be able to work closely with our hardworking and experienced engineers to help design groundbreaking technology. You will gain knowledge and tackle challenges while being able to encounter opportunities to work on all aspects of product development. 

    We want to make sure that every intern learns about different aspects of our work and grows their knowledge, that is why you will work in a team on real projects from day one, with guidance from expert engineers, and also have dedicated time for personal development. 


    Meeting Area, Frequency, and Power requirements with a reasonable runtime is one of most challenging activities we encounter when developing CPUs.

    On the soft IP market, we must also be as realistic as possible to ensure a good correlation with real silicon. 

    As Implementation engineers, we work with advanced EDA tools to model real physical environments of CPUs while targeting aggressive goals on advanced process nodes (7nm and below). 

    Join us and influence CPUs design, implementation methodology, and basic building block architecture (RAMs and standard cells). 

    Several subjects are available and described below. Choose the one(s) you prefer and indicate them in your application. Only one student will work on a given subject, followed by a dedicated expert engineer.



    Power consumption is a key parameter for all CPUs. 

    There are many ways to achieve low power and all of them will impact other key parameters such as area or frequency. 

    This internship will look at both modifying the CPU microarchitecture and using implementation flow features to improve dynamic and static power. 

    Using leading edge tools and methodology, you will analyse microarchitecture changes such as clock gating or data gating and find the correct trade-off to not impair frequency. 

    You will also investigate state-of-the-art CPU implementation flows and propose/adjust settings to obtain extra power benefits. 

    With this internship, you will have the opportunity to gain both knowledge on design for power efficiency and CPU implementation flow 



    Pushing frequency, power efficiency, and optimizing area of a specific RTL IP is a central task in CPU development. 

    The goal of this internship is to set up and analyse the results of several CPU implementation flows from different tool vendors. The expected end results are comparative strengths and weaknesses of the studied variants. 

    With this internship, you will have the opportunity to learn CPU implementation flows in depth by adapting and using state-of-the art implementation flow from several tool vendors. 

    While interacting with skilled implementation engineers and EDA tool vendors, you will be responsible for getting the best possible results out of each flow on the next generation CPU. 

    You will have to examine the results compare them to reference data, and clearly articulate benefits and drawbacks of each approach. 

    Metrics to be analysed contain, among others, frequency, area, dynamic and static power consumption, routing congestion and errors, runtime, memory usage, and ease of use for PPA debug. 


    At the crossroad between CPU design, CPU implementation, and CPU Design For Test, you will have to compare area/frequency of storage structures using either DFF, RAMs, or latches. 

    During this internship, you will:

    -        Understand existing CPU storage units using either DFF or RAMs.

    -        Evaluate which one can be replaced by latch-based storage.

    -        Understand MBIST interfaces and connections and how it can be used to test latch-based storage.

    -        Propose code in Verilog and analyse area trade-off for different variants of this test interface, including in-depth analysis on how to implement efficiently a latch array.

    With this internship, you will have the opportunity to do both Verilog coding and physical implementation on a next generation CPU.



    Job Requirements


    We are looking for students in their last year of Masters (BAC+5 or equivalent) and available for a 5-month or 6-month internship.

    We are looking for students in electronic engineering, computer engineering, computer science, or another relevant field, but other degrees may also be considered based on your experience. 

    We are looking for students who have the following skills or experience:

    • An engineering mind-set with strong problem-solving skills.
    • A keen interest in CPUs and digital systems.
    • An understanding of computer architecture fundamentals.
    • Familiarity with basic digital design concepts.
    • Experience with at least one programming language.
    • Excellent attention to detail.
    • Creativity and ability to communicate ideas effectively.
    • Good interpersonal and collaboration skills.


    • Knowledge of one of the main CPU architectures.
    • Knowledge of design techniques for low power.
    • Exposure or knowledge on synthesis, place and route tools and techniques.
    • Understanding of Power/Performance/Area trade-off in typical CMOS designs.
    • Familiarity with a hardware description language such as VHDL or Verilog/SystemVerilog.
    • Familiarity with versioning environment such a git.
    • Use of a Linux environment and shell programming/scripting, for example. bash, git, or make.


    Salary – 1750 euros / month

    Lunch vouchers

    1 day off (authorized leave) / month


    Internship duration

    5 to 6 months.


    ARM Benefits


    Your particular benefits package will depend on position and type of employment and may be subject to change. Your package will be confirmed on offer of employment. Arm’s benefits program provides permanent employees with the opportunity to stay innovative and healthy, ensure the wellness of their families, and create a positive working environment.

    • Annual Bonus Plan
    • Discretionary Cash Award
    • Supplementary pension
    • Private Medical Insurance (employee & family)
    • Life Insurance
    • Holiday, 25 days annual leave
    • Sabbatical, 20 paid business days every four-years of service
    • Volunteering, One (1) paid working day each year (TeamARM)
    • Others, free car parking, luncheon vouchers & Public Transport Pass reduction, team and social events

    About Arm

    Arm® technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. From the unmissable to the invisible; our advanced, energy-efficient processor designs are enabling the intelligence in 86 billion silicon chips and securely powering products from the sensor to the smartphone to the supercomputer. With more than 1,000 technology partners including the world’s most famous business and consumer brands, we are driving Arm innovation into all areas compute is happening inside the chip, the network and the cloud.

    With offices around the world, Arm is a diverse community of dedicated, innovative and highly talented professionals. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we encourage our people to share their unique contributions to Arm's success in the global marketplace.

    About the office

    The staff at the Arm Sophia Antipolis design center is mostly focused on CPU design. Sophia Antipolis is a technology park that’s surrounded by a large national park, with wild boar that live within the city and can be seen strolling through the tech park. It’s conveniently located a quick 30 minute drive southwest of Nice, 45 minutes to Monaco, and only 20 minutes to Cannes.

    Sophia Antipolis, France
    Arm France SAS
    25 Allée Pierre Ziller
    Le Paros
    BP 70124
    F-06903 Sophia Antipolis Cedex

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