In this role, you will support leading semiconductor design houses implement advanced Arm cores/subsystems in their nanometer SoC designs meeting aggressive performance, power, and area (PPA) requirements. You will work with Arm design engineers using the latest EDA tools/flows as well as latest foundry process nodes to put together best-in-class physical IP libraries (logic, memory, I/O) optimized for our latest advanced core and cluster architectures. You will work with Arm technical documentation groups to enhance our user guides and application/methodology notes in enabling our customers to easily acquire and deploy our physical IP for faster time to silicon. You will represent customer requirements to Arm product groups based on service requests, trends, defects, benchmarking, etc. and will be the main Arm technical interface to current/future Arm customers.
With the ever-increasing complexity associated with implementing multi-core DVFS clusters in finFET processes, we need a seasoned individual with good understanding of the low-level details (device, cell, memory, layout, Verilog, interconnect, timing, power, test, variation/etc.) coupled with some understanding of high-level EDA flows deployed in IC design. This experienced professional shall demonstrate proven ability for solving complex IC design challenges with considerations for library/cell selection, cell/memory architecture tradeoffs, process variants and their PPA tradeoffs, on chip variation, advanced modeling, margining methodologies, foundry requirements, etc. in supporting our customers realize the best quality of results from our RTL by offering guidance, training, and support services till tape out. Arm’s IP portfolio expansion from mobile computing into AI, automotive, Infrastructure, IOT and other market segments resulted in consistent growth beyond the semiconductor industry averages, resulting in career advancement opportunities previously unseen in traditional design houses. Here is your chance to leverage that growth to advance your career at Arm.
What will I be accountable for?
• Work with Arm physical IP library teams designing logic, memory, and IO offerings
• Customer support, training and design services related to our library IP products
• Answer queries from simple library usage to complex silicon debug and characterization issues
• Creation of application notes, white papers and training collateral
• Continually improve product documentation to maximize customer satisfaction
• Support sales and marketing teams with competitive benchmarking of physical libraries
• Interface with foundries for PDK revisions, customer silicon issues, waivers, etc.
• Work with geographically diverse engineering and support teams to deliver Arm quality customer support