Job Description

The Staff Layout Designer will work in support of ARM’s high performance standard cell design activities. Responsibilities to include the layout of standard cell libraries while working in highly structured design flows.

Job Requirements

Purpose

The Staff Layout Designer will be responsible for the development of standard cell libraries in a wide variety of different processes targeting all extremes of power, performance, and density.  The Staff Layout Designer will work as part of a small team to create custom layout and then verify its quality through floor planning and routing experiments using a variety of industry standard tool flows.

Key Accountabilities

   * Expertise in high density layout techniques especially as regards standard cells
   * Expertise with layout verification tools
   * Experience with industry standard floor planning and routing tools
   * Mentorship of other members of the mask design team
   * Schedule layout tasks for a small team within the framework of a short duration projects

Personal Specification

The ideal candidate is expected to have 5+ years high density mask design experience and will have experience mentoring and leading other mask designers.  The ideal candidate will also be experienced with one or more modern industry standard routers and floor planning flows.

Education
   * Qualified candidates will preferably have a university degree(s) in Electronic Engineering, Computer Engineering or other relevant technical discipline.
The ideal candidate is expected to have 5+ years relavent layout design experience
   * Formal training in VLSI design is considered a plus, but is not a requirement

Experience

   * Qualified candidates will have five or more years of experience creating high density layout and at least one year of experience using routing and floor planning tools

Specifically, candidates should have:

   * Specific familiarity with 20nm, 14nm or smaller feature size processes
   * Expertise with Cadence Virtuoso
   * Expertise with layout verification tools, preferably Mentor Graphics Calibre
   * Experience with state of the art place and route design tools, preferably Astro
   * Ability to read schematics and convert them to layout
   * Ability to interpret and follow complex process design, electrical, and reliability rules
   * Understanding of layout parasitics and how to minimize their impact on a designs performance
   * Ability to pay extreme attention to details with high levels of consistency being an absolute requirement
   * Experience in development of schedules for a team and leading a team to meet that schedule, including recommending necessary resource adjustments over time to the resources to maintain schedules for short duration projects
   * Ability to recognize general layout solutions and apply them to large classes of circuit designs


Other relevant skills include:

   * Ability to mentor more junior members of the design team on layout oriented issues including custom mask design, floor planning, and routing
   * Ability to coordinate a multi-disciplinary team working from different design centers
   * Experience writing LEF technology files
   * Experience writing Milkyway technology files
   * Experience writing Calibre decks for LVS and DRC
   * Experience writing Skill programs for using in Cadence DFII
   * Familiarity with 28nm, 20nm or smaller feature size processes


General Attributes

It is essential for the successful applicant to:

   * Co-operate & communicate well with library development team.
   * Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center's success
   * Demonstrate a positive attitude and respect for all members of the team

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