Job Description

Introduction :
ARM offers IC designers a wide range of choices from its broad portfolio of standard cell, memory, and I/O products. The ARM product line is optimized for each silicon technology. ARM's Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM products have been used in circuits running as fast as 2GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 28nm and 20nm semiconductor processes for various foundries and IDMs.  
Our circuit group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with a very successful circuit and layout team. The team has exposure to a wide variety of design rules from leading edge foundries as well as design teams from many of the world’s leading developers of digital ICs making for an ideal learning environment.
Job Purpose :
The Standard Cell Design Engineer will be responsible for the development of standard cell libraries in a wide variety of different processes targeting all extremes of power, performance, and density.  The Standard Cell Design Engineer will work as part of a  small team to optimize schematics, develop layout, drive the mask design team, characterize the cells, generate all standard library views, and verify all views by exercising them using a variety of industry standard tool flows.
Accountabilities / Responsibilities :

• Circuit design of standard cells including traditional logic cells as well as advanced power management cells
  
• Verification of functionality, performance & power of developed circuits
  
• Characterization of the Cell library
  
• Generation of all views delivered with our Physical IP product lines
  
• Testing of all views by exercising them in several industry standard design flows
  
• Good understanding of layout to effectively drive the mask design team and perform layout development tasks
  
• Understanding of deep submicron device physics in order to account for these non-ideal effects during cell design
  
• Understanding or an ability to learn a wide variety of industry standard modelling formats including:Liberty (CCS and NLM), Verilog, LEF, Milkyway, Spice, ECSM, and CDB
  

Job Requirements

Essential Skills & Experience
Specifically, candidates should have:

• An understanding of MOSFET electrical characteristics
  
• An understanding of power, performance, and area tradeoffs
  
• Understanding of layout at the transistor level
  
• Understanding of Design For Manufacturability (DFM) layout techniques
  
• Experience with transistor level circuit simulators
  
• Experience with Schematic and  Layout Capture: Cadence schematic or equivalent.
  
• Experience with backend verification tools: DRC, LVS (HERCULES, CALIBRE, ICV)
  
• Experience with LEF and Milkyway view formats
  
• Understanding of extraction methodologies and limitations
  
• Diagnostic skills for tools and resultant reports
  
• Knowledge of shell/tcl/Perl  scripting
  
• Basic Source control management with tool such  DesignSync
  

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