Job Description

Background
ARM offers IC designers a wide range of choices from its broad portfolio of Artisan memory products. The Artisan high-performance, high-density, low-power and ultra low-power memory generators are optimized for each silicon technology. ARM's Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM memory products have been used in circuits running as fast as 1GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 32nm, and 28nm semiconductor processes for various foundries and IDMs. Our memory group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital layout professional to work with the world’s most successful circuit and layout team with exposure to a wide variety of design rules from leading edge foundries.


Role
A candidate will be responsible for these tasks:
• Work with the layout designers for San Jose Memory Product group
• Work with ARM engineers to define memory product layout architecture
• Evaluate design rule tradeoffs for IC manufacturers (foundries and IDMs)
• Experiment and evaluate new layout architectures
• Contribute in  layout procedures and techniques
• Ensure high quality, high performance in memory layouts
• Work with other layout resources to continually define, improve and develop layout infrastructure and methods
• Utilizing advanced CAD tools, mask design knowledge to layout correct and robust physical design representation of circuits.

Job Requirements

Personal Requirements
• College degree or Graduate from layout technical school

Essential Technical Skills

• 6+  years layout experience drawing memory compilers with good knowledge of hierarchical layout planning
• Layout experience with deep submicron technologies (28nm or smaller)
• Fundamental understanding of Design For Manufacturability (DFM) layout techniques
• Familiarity with Cadence Virtuoso (DFII, Opus) layout environment and UNIX.
• Must have good understanding on layout optimization, core-array development, physical verification and reliability checks at leaf-cell level and instance level.
• Able to independently address EM/IR issues and fix layout accordingly
• Ability to accurately plan and schedule responsibilities
• Demonstrable scripting/automation capabilities to improve productivity
• Experience in instance level back end verification.

Desirable Skills

• Experience working with place & route chip design tools
• Programming or scripting experience
• Reading and understanding DRC/LVS run sets.



Personal Skills

• Enthusiastic, self-motivated, flexible with strong inter-personal skills
• High degree of initiative
• Willingness and ability to contribute to process improvement initiatives
• Demonstrate a positive attitude and respect for all members of the team
• Good communication skills, oral and written

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