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Job Details
Senior Standard Cell Engineer
Job ID #: 3600
Country: USA Location: Austin (TX)
Job Category: Design Engineering Employment Type: Experienced Professionals
Division: Physical Design Department:
Hours of work (per week):



Introduction

ARM offers IC designers a wide range of choices from its broad portfolio of standard cell, memory, and I/O products. The ARM product line is optimized for each silicon technology. ARM's Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM have been used in circuits running as fast as 2GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 32nm, 28nm, and 20nm semiconductor processes for various foundries and IDMs.

Our circuit group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with the world’s most successful circuit and layout team with exposure to a wide variety of design rules from leading edge foundries. The team has exposure to a wide variety of design rules from leading edge foundries as well as design teams from many of the world’s leading developers of digital ICs making for an ideal learning environment.

Job Purpose
The engineer will be responsible for the development of standard cell library schematic source in a wide variety of different processes targeting all extremes of power, performance, and density. The engineer will support the design of cutting-edge standard cells that enable low power and high density libraries. The engineer will also work as part of a small team in close cooperation with the design automation team to improve the standard tool tuning and design assurance flows.

Accountabilities / Responsibilities

  • Circuit design of standard cells including traditional logic cells as well as advanced power management cells
  • Maintenance of standard cell schematic source
  • Updating standard cell design assurance flows in cooperation with the design automation team
  • Verification of functionality, performance, and power of developed circuits
  • Understanding of deep submicron device physics in order to account for these non-ideal effects during cell design



Essential Skills & Experience

  • 4+ years of relevant circuit design experience (for BSEE)
  • 2+ years of relevant circuit design experience (for MSEE)
  • A solid understanding of MOSFET electrical characteristics
  • An understanding of transistor level device physics
  • Experience with transistor level design of static circuits including state retaining elements like latches and flops
  • An understanding of power, performance, and area tradeoffs
  • An understanding of layout at the transistor level
  • Experience with transistor level circuit simulators
  • An understanding of programming in order to automate tasks


Desirable Skills & Experience
  • An understanding of extraction methodologies and limitations
  • Diagnostic skills for tools and resultant reports
  • Experience with Synthesis, Place, and Route flows



Interpersonal Skills
It is essential for the successful applicant to:
  • Cooperate and communicate well with the library development and design automation
  • Be motivated to continuously develop skills and accept a variety of responsibilities as a part of contributing to the design center’s success
  • Demonstrate a positive attitude and respect for all members of the team
  • Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems



Package
ARM will offer the following benefits for this position:
  • Salary - Commensurate with experience
  • Equity
  • Bonus Plan
  • Medical Insurance
  • Dental Insurance
  • Life Insurance
  • Contributory 401K
  • 4 weeks paid vacation
  • 4 weeks paid sabbatical every 4 years


ARM is an equal opportunity employer.

LI*JG

We are an Equal Opportunity Employer and do not discriminate against applicants due to race, ethnicity, gender, veteran status, or on the basis of disability or any other federal, state or local protected class.

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