Introduction ARM offers IC designers a wide range of choices from its broad portfolio of Artisan memory products. The Artisan high-performance, high-density, low-power and ultra low-power memory generators are optimized for each silicon technology. ARM's Artisan Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM memory products have been used in circuits running as fast as 1GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm and 65nm semiconductor processes for various foundries and IDMs. Our circuit group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with the world’s most successful circuit and layout team with exposure to a wide variety of design rules from leading edge foundries. Accountabilities / Responsibilities
Contribute in all parts of Advance Product Memory development flow, starting at design spec Understand Memory design and development, analysis memory marginality in advance technology (45nm and beyond) Understand and perform physical verification, memory characterization, FE verification, release procedure and QA flow of the memory compilers Experiment and evaluate new memory architectures and methodologies Work with senior resources to continually define, improve and develop memory infrastructure and methods Ensure high quality, high performance in memory compilers
Essential Skills & Experience 8 - 10 years of relevant circuit design experience (for BSEE) 6 - 8 years of relevant circuit design experience (for MSEE) Circuit design experience with memory compilers Circuit/Layout experience with deep submicron technologies (90nm or smaller) Fundamental understanding of technology tradeoffs in deep sub-micron design Fundamental understanding of Design For Manufacturability (DFM) layout techniques Familiarity with Cadence Virtuoso (DFII, Opus) layout environment Experience in low power circuit techniques Desirable Skills & Experience Experience working with place & route chip design tools Experience with layout automation tools, such as Prolific, Cadabra, Qtrek Experience with other EDA tools such as design_compiler, Astro, Physical Compiler, PrimeTime, SoC Encounter, Pacific, Nanosim, Pathmill, Spectre, HSPICE, etc Programming or scripting experience Coding, modifying, or reading DRC/LVS runsets Interpersonal Skills Enthusiastic, self-motivated, and flexible High degree of initiative Willingness and ability to contribute to process improvement initiatives Good communication skills, oral and written Package ARM will offer the following benefits for this position: Salary - Commensurate with experience Equity Medical Insurance Dental Insurance Life Insurance Contributory 401K 4 weeks paid vacation ARM is an Equal Opportunity Employer.