Job Description

Job Description
Job Purpose
In this role, the candidate will be responsible for unit-level verification of RTL blocks which comprise the next-generation ARM enterprise processor.

This is an outstanding opportunity to be part of the ARM Austin Design Center. Our main focus is designing high-performance processor, interconnect, and system IP.  You will be part of a small and talented team, giving you the opportunity to innovate and make a significant contribution. We employ leading-edge technologies and methodologies to ensure the highest quality in our products.
 
Responsibilities

• Develop SystemVerilog testbenches for block-level functional verification of the CPU pipeline and memory system.
  
• Document testplans and testbench design.
  
• Generate and run testcases on logic simulation models.
  
• Debug and correct functional errors in the HDL/logic model, using simulation tools, debug tools, and programming skills, based on in-depth understanding of the architecture and RTL design of the processor.
  
• Define and implement functional coverage, enhance testbench to ensure coverage closure.
  

Job Requirements

Job Requirements
Experience
The candidate should have 5+ years experience in microprocessor validation including focused experience in the area of coherent memory systems and/or out-of-order microarchitecture.

Skills & Experience
Applicants should have experience in most of the following areas:

• CPU memory system microarchitecture, including high-performance caches, out-of-order execution and result return, cache coherence, virtual memory and address translation, system bus interfaces.
  
• CPU microarchitecture including knowledge of out-of-order execution, register renaming, reservation stations, processor pipelines, etc.
  
• Verilog HDL language and associated software simulators
  
• Assembly language for ARM or other architectures
  
• Understanding of logic design, state machines, etc.
  
• Good software engineering skills including understanding of object-oriented programming, data structures, and algorithms
  
• Specification and creation of design testbenches
  
• Functional coverage driven verification methods
  

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