Job Description

Introduction:

ARM is a state-of-art company providing high-performance, high-quality, and low-power CPUs and Physical Libraries to world's leading chip and device manufacturers like IBM, TI, AMD, Intel, Samsung, and Nokia to name a few.
The Physical IP Organization inside ARM creates Physical IPs of various types like Standard Cells, Memory, IO which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180 nm to 32nm and research work on 22nm solutions is happening at various ARM design centers worldwide.
Job Purpose:
The role will involve: implementing ARM Cores like CortexA9, CortexM3, Mali 200 etc for the purpose of benchmarking and validating the libraries; developing, verifying and validating the routing techfiles; driving the implementation, integration, and verification effort of the block and top level; Communicating place and route strategies, floor plan, clock tree implementation, power grid structure, interfacing with analog/mix signal block across other team members; Working with marketing, engineering based in other sites to get an optimal PPA for ARM Cores like CortexA9. The business unit is an outward-looking organization that encourages contact between its engineers and those of customers.
Accountabilities / Responsibilities:

Candidates should be experts in their field and have some experiences on project management and will be working on Benchmarking of ARM Cores. Candidates should be able to mentor junior engineers as well as lead them technically for the successful completion of projects.
This includes

• Synthesis of RTL to Netlist
  
• Setting timing constraints for  place and route
  
• Digital block place and route with complex multi clock designs
  
• Proper floor planning according to timing and power requirement
  
• Resolving placement and routing congestion issues
  
• Providing detailed feedback to the RTL team on opportunities for improvement of the micro-architecture to aid implementation
  
• Provision of feedback on block specifications
  
• Development of design guidelines for speed and SI
  
• Clock tree synthesis
  
• Power grid implementation
  
• Power IR drop analysis
  
• Close timing in both block and top level with predictable result and schedule
  
• Implement DFM for place and routed block
  
• Implement ECO
  
• Top level integration of all necessary blocks
  
• Run RC extraction and close timing based on post layout netlist
  
• Finish drc, lvs on the place and route block and resolve drc and lvs related issues
  
• Write automation script to enable repeatable P&R process
  
• Write technical documentation
  

Job Requirements

Job Requirements

Education & Qualifications:

• BSEE/CS Required
  
• MSEE/CS Preferred
  

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