Job Description

ARM Introduction

If you have a smartphone, digital camera, digital TV, gaming console or a smart meter at home, you’ve already used an ARM Powered product. Over 125 ARM Powered products are shipped every second and over 35 billion ARM technology-based chips have been shipped to date making us the world’s leading Intellectual Property (IP) semiconductor supplier.

We see a world where billions of people can collaborate, communicate and connect every day. Improving people’s lives by enabling access to affordable, easy to use intelligent electronic products and services which transform the way we live and work.

We’re at the heart of driving the future of our digital world, as we build and support collaborative and open relationships. Working side by side with the leading technology companies across the globe we design and license IP to enable them to innovate. Together with our partners, it is ARM technology that is enhancing the lives of over six billion people connected in the world today.

Graduate Opportunities

The aim of our Graduate Development Programme is to develop your potential and expand the opportunities on offer to you – giving you an incredible variety of potential career paths. We’ll support you with continuous learning and development through a blend of on the job and formal training, mentoring and a knowledge network while encouraging you to achieve professional chartered status.

Together, we will shape the lifestyles of the next billion people in a better world – one that’s always-on, always-connected.

Introduction

ARM offers IC designers a wide range of choices from its broad portfolio of standard cell, memory, and I/O products. The ARM product line is optimized for each silicon technology. ARM's Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM products have been used in circuits running as fast as 2GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 28nm and 20nm semiconductor processes for various foundries and IDMs.  

Our layout group comprises some of the industry’s leading experts in deep submicron layout design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a memory layout professional to work with the world’s most successful layout team with exposure to a wide variety of design rules from leading edge foundries, in particular on the SOI technology.

Job Purpose

The Graduate Memory Layout Engineer will be part of the layout team to develop memory compiler in a wide variety of different processes. The Graduate Memory Layout Engineer will also get involved in validation and verification task as DRC/LVS/Extraction/IR/EM/P&R validations.

Key Accountabilities/Responsibilities

• Participate in the memory compiler layout developments for ARM’s Europe Physical IP Design Centers (Grenoble and Cambridge).
• Participate in the memory compiler layout physical validation (DRC/LVS/DFM/IR/EM)
• Participate in the memory compiler view validation (lef, milkyway) with place & route tools
• Evaluate design rule tradeoffs for IC manufacturers (foundries and IDMs)
• Contribute in layout procedures and techniques
• Ensure high quality, high performance in IP layouts
• Participate in improvement  and development layout infrastructure and methods
And could be involved for any combination of these tasks:
• Create automation for layout procedures
• DRC/LVS runset modification
• Internal development flow setup associated to above accountabilities

Job Requirements

Education & Qualifications
Qualified candidates will have a university degree(s) in Electronic Engineering, Computer Engineering or other relevant technical discipline.

Essential Skills & Experience

• 0-2 years of industry experience in layout implementation for memory compilers
• Layout experience with memory compilers and/or standard cells libraries and/or IO libraries
• Layout experience with deep submicron technologies (0.65 or smaller)
• Fundamental understanding of Design For Manufacturability (DFM) layout techniques
• Familiarity with Cadence Virtuoso (DFII, Opus) layout environment

Desirable Skills & Experience

• Experience designing memory compilers is a plus
• Familiarity with Cadence Pcells  and VirtuosoXL layout environment
• Experience working with place & route chip design tools
• Programming or scripting experience (Cadence Skill)
• Coding, modifying, or reading DRC/LVS runsets

Personal Skills

• Capable of working as a hands-on layout contributor
• Enthusiastic, self-motivated, flexible with strong inter-personal skills
• Willingness and ability to contribute to process improvement initiatives
• Good communication skills, oral and written

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